Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F07%3A03130529" target="_blank" >RIV/68407700:21230/07:03130529 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System
Original language description
The implementation and the fault emulation technique for the highly reliable digital design using Modified Duplex System (MDS) architecture under a processor control is presented. A Totally Self-Checking analysis of MDS architecture is supported by experimental results from our proposed FPGA fault emulator, where SEU-fault resistance is observed. Our proposed hardware fault emulator results are compared also with the software simulation results. An area overhead of individual parts implemented in each FPGA is also discussed.
Czech name
Injekce a simulace poruch pro rekonfigurovatelný duplexní systém odolný proti poruchám
Czech description
Popis metody injekce a simulace poruch pro rekonfigurovatelný duplexní systém odolný proti poruchám.
Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
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Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2007
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Design and Diagnostics of Electronic Circuits and Systems
ISBN
1-4244-1161-0
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
357-360
Publisher name
IEEE Computer Society
Place of publication
Los Alamitos
Event location
Krakow
Event date
Apr 10, 2007
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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