An FPGA based fault emulator
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F07%3A03133257" target="_blank" >RIV/68407700:21230/07:03133257 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
An FPGA based fault emulator
Original language description
An FPGA hardware fault emulator is presented. The emulator performs a single-bit fault injection in bitstream on top of the implemented circuit, emulating the SEU event. The combinatorial circuits mapped in FPGA are tested and SEU-fault resistance is observed.
Czech name
An FPGA based fault emulator
Czech description
An FPGA hardware fault emulator is presented. The emulator performs a single-bit fault injection in bitstream on top of the implemented circuit, emulating the SEU event. The combinatorial circuits mapped in FPGA are tested and SEU-fault resistance is observed.
Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
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Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2007
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the Work in Progress Session held in connection with the EUROMICRO Conferences SEAA and DSD 2007
ISBN
978-3-902457-16-5
ISSN
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e-ISSN
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Number of pages
2
Pages from-to
42-43
Publisher name
Johannes Kepler University
Place of publication
Linz
Event location
Lübeck
Event date
Aug 27, 2007
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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