SEU Simulation Framework for Xilinx FPGA: First Step Towards Testing Fault Tolerant Systems
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F11%3APU96032" target="_blank" >RIV/00216305:26230/11:PU96032 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
SEU Simulation Framework for Xilinx FPGA: First Step Towards Testing Fault Tolerant Systems
Original language description
In the paper, the SEU simulation framework for testing fault tolerant system designs implemented into FPGA is presented. The framework is based on SEU generation outside FPGA (in personal computer) and the transport of modified bitstream through the JTAGinterface and subsequent dynamic reconfiguration of FPGA. It allows to select region of the FPGA for SEU placing. The SEU simulator does not require any changes in the tested design and is fully independent on the function implemented into FPGA. Therequirements on the SEU generator and its properties are described in the paper as well. The external SEU generator for Xilinx FPGA was implemented and verified on evaluation board ML506 with Vitrex5 for different types of RTL circuits and fault tolerant architectures. The experimatal results demonstrated the effectiveness of the methodology.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
IN - Informatics
OECD FORD branch
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Result continuities
Project
<a href="/en/project/GA102%2F09%2F1668" target="_blank" >GA102/09/1668: SoC circuits reliability and availability improvement</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2011
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
14th EUROMICRO Conference on Digital System Design
ISBN
978-0-7695-4494-6
ISSN
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e-ISSN
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Number of pages
8
Pages from-to
223-230
Publisher name
IEEE Computer Society
Place of publication
Oulu
Event location
Oulu
Event date
Aug 31, 2011
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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