Experimental SEU Impact on Digital Design Implemented in FPGAs

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F08%3A00147000" target="_blank" >RIV/68407700:21230/08:00147000 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Experimental SEU Impact on Digital Design Implemented in FPGAs
Original language description
The main aim of our research is to investigate the influence of SEU on a digital circuit implemented in FPGA. The FPGA resources occupied by design are divided into several groups. SEU impact is investigated for each group. To make a real dependability model the real effects of injected errors and faults have to be studied. The SEU emulator deals with single-bit change in bitstream. Emulation is performed in the user-selected area. Look-Up-Tables, cell interconnections, cell-to-bus connections and routing resources are considered. Other FPGA resources are not considered. Combinatorial circuits and MCNC benchmarks were measured due to our knowledge of FPGA resource limitation. All tests were performed on Atmel FPSLIC architecture.
Czech name
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Czech description
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Project
<a href="/en/project/FI-IM4%2F149" target="_blank" >FI-IM4/149: *Research and Development of High-rate Microwave Line Featured by QAM Modulation and the Transmission Speed of 155 Mbit/s.</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year
2008
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of 11th Euromicro Conference on Digital System Design
ISBN
978-0-7695-3277-6
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
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Publisher name
IEEE Computer Society
Place of publication
Los Alamitos
Event location
Parma
Event date
Sep 3, 2008
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000264279400014

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