Hardware Acceleration for Computational Intelligence - THSOM Neural Network on x86 hardware

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F08%3A00146974" target="_blank" >RIV/68407700:21230/08:00146974 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Hardware Acceleration for Computational Intelligence - THSOM Neural Network on x86 hardware
Original language description
This paper presents an accelerated simulation of a Temporal Hebbian Self-organizing map (THSOM) neural network on x86 based platform. To reduce the time, our implementation utilizes all parallel features of modern x86 hardware - The data parallelism using the SIMD SSE instruction set and instruction parallelism utilizing multiple cores. The overall design of our THSOM implementation is modular, allowing us to re-implement specific parts of computations with different optimizations or parallel approachesyet still maintain good comparability between different optimizing combinations. We present the results of our measurements and influence of data parallel and instruction parallel processing compared to differently optimized versions. We also present anefficient method for frequent barrier synchronization of different threads.
Czech name
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Czech description
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Publication year
2008
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
European Simulation and Modelling Conference 2008
ISBN
978-90-77381-44-1
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
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Publisher name
EUROSIS - ETI
Place of publication
Ghent
Event location
Le Havre
Event date
Oct 27, 2008
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000264749400048

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