Fast Boolean Minimizer for Completely Specified Functions

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F08%3A03142125" target="_blank" >RIV/68407700:21230/08:03142125 - isvavai.cz</a>

Alternative codes found

RIV/67985556:_____/08:00312223

Result on the web

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DOI - Digital Object Identifier

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Result language

angličtina

Original language name

Fast Boolean Minimizer for Completely Specified Functions

Original language description

We propose a simple and fast two-level minimization algorithm for completely specified functions in this paper. The algorithm is based on processing ternary trees. A ternary tree is proposed as a structure enabling a very compact representation of completely specified Boolean functions. It is efficient especially for functions having many on-set terms. The minimization algorithm is thus most suited for functions described by many on set terms. Such functions emerge as a result of many algorithms used inlogic synthesis process, e.g., multi-level network collapsing, algebraic manipulation with logic functions, etc. When these functions are to be minimized, most of the state-of-the-art minimizers (Espresso) need prohibitively long time to process them, or they are even completely unusable, due to their very high memory consumption. Our algorithm is able to minimize such functions in a reasonable time, though the result quality does not reach the quality of other minimizers.

Czech name

Fast Boolean Minimizer for Completely Specified Functions

Czech description

We propose a simple and fast two-level minimization algorithm for completely specified functions in this paper. The algorithm is based on processing ternary trees. A ternary tree is proposed as a structure enabling a very compact representation of completely specified Boolean functions. It is efficient especially for functions having many on-set terms. The minimization algorithm is thus most suited for functions described by many on set terms. Such functions emerge as a result of many algorithms used inlogic synthesis process, e.g., multi-level network collapsing, algebraic manipulation with logic functions, etc. When these functions are to be minimized, most of the state-of-the-art minimizers (Espresso) need prohibitively long time to process them, or they are even completely unusable, due to their very high memory consumption. Our algorithm is able to minimize such functions in a reasonable time, though the result quality does not reach the quality of other minimizers.

Type

D - Article in proceedings

CEP classification

JC - Computer hardware and software

OECD FORD branch

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Project

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Continuities

Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year

2008

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

Proc. of 11th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop 2008 (DDECS'08)

ISBN

978-1-4244-2276-0

ISSN

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e-ISSN

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Number of pages

6

Pages from-to

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Publisher name

IEEE Computer Society Press

Place of publication

Los Alamitos

Event location

Bratislava

Event date

Apr 16, 2008

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

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