A Fast SOP Minimizer for Logic Funcions Described by Many Product Terms

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F09%3A00157235" target="_blank" >RIV/68407700:21240/09:00157235 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
A Fast SOP Minimizer for Logic Funcions Described by Many Product Terms
Original language description
We introduce a fast and efficient minimization method for functions described by many (up to millions) product terms. The algorithm is based on processing a newly proposed efficient representation of a set of product terms - a ternary tree. A significantspeedup of the look-up of the term operation is achieved, with respect to a standard tabular function representation. The minimization procedure is based on a fast application of basic Boolean operations upon a ternary tree. Minimization of incompletelyspecified functions is supported as well. The minimization method was tested on randomly generated large sums-of-products, collapsed ISCAS benchmark circuits and SAT problems. The performance of the proposed algorithm was compared with Espresso.
Czech name
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Czech description
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Project
<a href="/en/project/GA102%2F09%2F1668" target="_blank" >GA102/09/1668: SoC circuits reliability and availability improvement</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year
2009
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proc. of 12th EUROMICRO Conference on Digital System Design
ISBN
978-0-7695-3782-5
ISSN
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e-ISSN
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Number of pages
8
Pages from-to
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Publisher name
IEEE Computer Society
Place of publication
Los Alamitos
Event location
Patras
Event date
Aug 27, 2009
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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