Versatile Sub-BandGap Reference IP Core

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F10%3A00173347" target="_blank" >RIV/68407700:21230/10:00173347 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Versatile Sub-BandGap Reference IP Core
Original language description
A step-by-step design procedure of sub-bandgap voltage reference (BGR) is proposed. The procedure shows on example structure main design steps of crucial parameters verified later by a simulation. The block is meant to be fabricated in 0.35um CMOS process with analog options. The main features of the concept are the sub-bandgap output voltage of 0.7V, low supply voltage from 1.3V, low power consumption under 10uA, versatility, high working temperature range from - 50 to 95 C. The versatility of the block is supported by a temperature slope trimming, extended start-up and self testing. The IP block is compact, ready to adjust, layout and integrate. The features of the design also allow the in circuit tuning. This example circuit shows the use of the design algorithm including the optimization suggestions which lead to a complex design.
Czech name
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Czech description
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Project
<a href="/en/project/GA102%2F07%2F1186" target="_blank" >GA102/07/1186: Sophisticated methods of the analog and mixed-signal circuits design in sub-micron technologies</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year
2010
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proc. of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems
ISBN
978-1-4244-6610-8
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
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Publisher name
IEEE
Place of publication
Piscataway
Event location
Vienna
Event date
Apr 14, 2010
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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