Hardware Architectures for Cryptanalysis
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F11%3A00176104" target="_blank" >RIV/68407700:21230/11:00176104 - isvavai.cz</a>
Alternative codes found
RIV/68407700:21240/11:00176104
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Hardware Architectures for Cryptanalysis
Original language description
In this work we explore the resistance of ciphers KeeLoq, Hitag-2, PRESENT and Cryptomeria against variants of brute-force attacks. The ciphers are dedicated for a Lightweight Cryptography, i.e. they find their application area in smartcards or car immobilizers. The ciphers KeeLoq, Hitag-2 and Cryptomeria are used in practice, while the cipher PRESENT has been designed as a replacement for outdated ciphers. We design hardware architectures for cryptanalysis of these ciphers. The architectures are implemented in FPGAs. Where possible, the Cost-Optimized Parallel Code Breaker COPACOBANA is used. The main contribution of this work will insist in (i) design of architectures supporting brute-force attack on individual ciphers and (ii) evaluation of the resistance against brute-force attacks for those ciphers.
Czech name
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Czech description
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Classification
Type
O - Miscellaneous
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
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Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach
Others
Publication year
2011
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů