Time-Area Efficient HW Architectures for Cryptography and Cryptanalysis

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F10%3A00167731" target="_blank" >RIV/68407700:21240/10:00167731 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Time-Area Efficient HW Architectures for Cryptography and Cryptanalysis
Original language description
The first part of the book focuses on hardware architectures operating over elements of GF(2^m) in normal basis representation. Such architectures are applicable e.g. in Elliptic Curve Cryptography. Four new architectures of digit-serial normal basis multipliers are presented. Based on these architectures, a novel structure of a normal basis arithmetic unit is proposed. As the unit is both small and scalable, the design constrains can be met optimally. The second part of the thesis focuses on the cryptanalysis of the A5/1 cipher used in GSM communications. Hardware architectures of two attacks against the A5/1 cipher are presented. The attacks have been implemented using an existing low-cost special-purpose hardware device: COPACOBANA. The attacks aredesigned to utilize both the properties of the cipher and the features of underlying reconfigurable hardware. Presented design approaches can be reused when designing attacks against similar ciphers.
Czech name
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Czech description
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Publication year
2010
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

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