An FPGA Implementation for ADC INL Measurement using the Servo-loop Method
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F11%3A00184437" target="_blank" >RIV/68407700:21230/11:00184437 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
An FPGA Implementation for ADC INL Measurement using the Servo-loop Method
Original language description
This paper deals with the new part of our testing environment for A/D converters and describes the FPGA implementation of the improved servo-loop algorithm. The article is focused especially on the algorithm function and features. FPGA resources and measurement time consumption are also briefly discussed.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
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Result continuities
Project
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Continuities
S - Specificky vyzkum na vysokych skolach
Others
Publication year
2011
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the 8th International Conference on Digital Technologies 2011
ISBN
978-80-554-0437-0
ISSN
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e-ISSN
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Number of pages
5
Pages from-to
194-198
Publisher name
Slovenská elektrotechnická společnost
Place of publication
Žilina
Event location
Žilina
Event date
Nov 10, 2011
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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