Power/Performance Trade-offs in Real-Time SDRAM Command Scheduling
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F16%3A00233103" target="_blank" >RIV/68407700:21230/16:00233103 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1109/TC.2015.2458859" target="_blank" >http://dx.doi.org/10.1109/TC.2015.2458859</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/TC.2015.2458859" target="_blank" >10.1109/TC.2015.2458859</a>
Alternative languages
Result language
angličtina
Original language name
Power/Performance Trade-offs in Real-Time SDRAM Command Scheduling
Original language description
Real-time safety-critical systems should provide hard bounds on an applications’ performance. SDRAM controllers used in this domain should therefore have a bounded worst-case bandwidth, response time, and power consumption. Existing works on real-time SDRAM controllers only consider a narrow range of memory devices, and do not evaluate how their schedulers’ performance varies across memory generations, nor how the scheduling algorithm influences power usage. The extent to which the number of banks used in parallel to serve a request impacts performance is also unexplored, and hence there are gaps in the tool set of a memory subsystem designer, in terms of both performance analysis, and configuration options. This article introduces a generalized close-page memory command scheduling algorithm that uses a variable number of banks in parallel to serve a request. To reduce the schedule length for DDR4 memories, we exploit bank grouping through a pairwise bank-group interleaving scheme. The algorithm is evaluated using an ILP formulation, and provides schedules of optimal length for most of the considered LPDDR, DDR2, DDR3, LPDDR2, LPDDR3 and DDR4 devices. We derive the worst-case bandwidth, power and execution time for the same set of devices, and discuss the observed trade-offs and trends in the scheduler-configuration design space based on these metrics, across memory generations.
Czech name
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Czech description
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Classification
Type
J<sub>x</sub> - Unclassified - Peer-reviewed scientific article (Jimp, Jsc and Jost)
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
<a href="/en/project/EE2.3.30.0034" target="_blank" >EE2.3.30.0034: Support of inter-sectoral mobility and quality enhancement of research teams at Czech Technical University in Prague</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2016
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Name of the periodical
IEEE Transactions on Computers
ISSN
0018-9340
e-ISSN
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Volume of the periodical
65
Issue of the periodical within the volume
6
Country of publishing house
US - UNITED STATES
Number of pages
14
Pages from-to
1882-1895
UT code for WoS article
000376879300016
EID of the result in the Scopus database
2-s2.0-84969821600