Optimization of PCB Assembly Process
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F16%3A00306695" target="_blank" >RIV/68407700:21230/16:00306695 - isvavai.cz</a>
Result on the web
<a href="http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7777242" target="_blank" >http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7777242</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/SIITME.2016.7777242" target="_blank" >10.1109/SIITME.2016.7777242</a>
Alternative languages
Result language
angličtina
Original language name
Optimization of PCB Assembly Process
Original language description
The goal of the optimization was to decrease the total time of assembly and the number of failures on assembled PCBs and to increase of quality and reliability of the boards. A mathematical model for this optimization was calculated. As tools for optimizing a six sigma, lean six sigma, theory of constrains and fuzzy logic were used.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
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Result continuities
Project
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Continuities
V - Vyzkumna aktivita podporovana z jinych verejnych zdroju
Others
Publication year
2016
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
2016 IEEE 22nd International Symposium for Design and Technology in Electronic Packaging (SIITME)
ISBN
978-1-5090-4446-7
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
55-58
Publisher name
IEEE
Place of publication
New York
Event location
Oradea
Event date
Oct 20, 2016
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000390557400007