Thermal Cycle Testing of Printed Circuit Board Vias (Barrel Plates)

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F18%3A00325945" target="_blank" >RIV/68407700:21230/18:00325945 - isvavai.cz</a>

Result on the web

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DOI - Digital Object Identifier

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Result language

angličtina

Original language name

Thermal Cycle Testing of Printed Circuit Board Vias (Barrel Plates)

Original language description

Printed circuit board (PCB) reliability is a very important factor from the point of total quality of output products. The ambient environment has influence on the reliability of PCBs and various issues can appear during its lifetime, even if the PCB properly passes the quality control before and after its assembly. This article deals with reliability test-monitoring of resistance behavior of the printed circuit board vias (barrel plates) during thermal stress (shock test). Appropriate printed circuit boards have been designed for this purpose. PCB sample was double-sided, vias were connected serially and PCB design allowed the use of four wire measurement method for measuring of all vias at once. The temperature sensor Pt100 was attached onto the PCB for better temperature monitoring of PCB during shock test. The shock test cycle took 20 minutes, the temperature of hot zone was set to 160 degrees C and the temperature of cool zone was -60 degrees C. The experiments help in understanding the barrel plate behavior during thermal stress, when the thermal expansion of composite substrate (glass-epoxy laminate) cause force (Young's modules), which stretches the barrel plate from the middle outwards. The identification of faulty vias is not easy during ambient temperature, it is easier when a measurement is conducted during thermal cycling or when the PCB is heated.

Czech name

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Czech description

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Type

D - Article in proceedings

CEP classification

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OECD FORD branch

20201 - Electrical and electronic engineering

Project

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Continuities

S - Specificky vyzkum na vysokych skolach

Publication year

2018

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

2018 41st International Spring Seminar on Electronics Technology (ISSE)

ISBN

978-3-319-73847-5

ISSN

2161-2536

e-ISSN

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Number of pages

4

Pages from-to

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Publisher name

IEEE

Place of publication

NEW YORK, NY

Event location

Zlatibor, Serbia

Event date

May 16, 2018

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

000449866600005