Combining PREM Compilation and Static Scheduling for High-Performance and Predictable MPSoC Execution

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F19%3A00328628" target="_blank" >RIV/68407700:21230/19:00328628 - isvavai.cz</a>

Alternative codes found

RIV/68407700:21730/19:00328628

Result on the web

<a href="http://hdl.handle.net/10467/87215" target="_blank" >http://hdl.handle.net/10467/87215</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1016/j.parco.2018.11.002" target="_blank" >10.1016/j.parco.2018.11.002</a>

Result language

angličtina

Original language name

Combining PREM Compilation and Static Scheduling for High-Performance and Predictable MPSoC Execution

Original language description

Many applications require both high performance and predictable timing. High-performance can be provided by COTS Multi-Core System on Chips (MPSoC), however, as cores in these systems share main memory, they are susceptible to interference from each other, which is a problem for timing predictability. We achieve predictability on multi-cores by employing the predictable execution model (PREM), which splits execution into a sequence of memory and compute phases, and schedules these such that only a single core is executing a memory phase at a time. We present a toolchain consisting of a compiler and a scheduling tool. Our compiler uses region and loop based analysis and performs tiling to transform application code into PREM-compliant binaries. In addition to enabling predictable execution, the compiler transformation optimizes accesses to the shared main memory. The scheduling tool uses a state-of-the-art heuristic algorithm and is able to schedule industrial-size instances. For smaller instances, we compare the results of the algorithm with optimal solutions found by solving an Integer Linear Programming model. Furthermore, we solve the problem of scheduling execution on multiple cores while preventing interference of memory phases. We evaluate our toolchain on Advanced Driver Assistance System (ADAS) application workloads running on an NVIDIA Tegra X1 embedded system-on-chip (SoC). The results show that our approach maintains similar average performance to the original (unmodified) program code and execution, while reducing variance of completion times by a factor of 9 with the identified optimal solutions and by a factor of 5 with schedules generated by our heuristic scheduler.

Czech name

—

Czech description

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Type

J_imp - Article in a specialist periodical, which is included in the Web of Science database

CEP classification

—

OECD FORD branch

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Project

—

Continuities

R - Projekt Ramcoveho programu EK

Publication year

2019

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Name of the periodical

Parallel Computing

ISSN

0167-8191

e-ISSN

1872-7336

Volume of the periodical

85

Issue of the periodical within the volume

July

Country of publishing house

NL - THE KINGDOM OF THE NETHERLANDS

Number of pages

18

Pages from-to

27-44

UT code for WoS article

000471087700003

EID of the result in the Scopus database

2-s2.0-85064278558