Implementation and Evaluation of Sum-Int ADC IP-core on NanoXplore FPGA

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F22%3A00359616" target="_blank" >RIV/68407700:21230/22:00359616 - isvavai.cz</a>
Result on the web
<a href="https://indico.esa.int/event/388/contributions/6724/" target="_blank" >https://indico.esa.int/event/388/contributions/6724/</a>
DOI - Digital Object Identifier
—

Result language
angličtina
Original language name
Implementation and Evaluation of Sum-Int ADC IP-core on NanoXplore FPGA
Original language description
The summing integration (SumInt) analog to digital conversion (ADC) technique combines and preserve many of excellent features of double integration and sigma-delta ADCs. It is well suited for application where integral of continuously sensed input signal carries information to acquire. It has been initially conceived at the PiKRON company for digitizing compounds responses measured by UV-VIS spectrophotometric detectors in high-performance liquid chromatography systems. The compound concentration in the sample is proportional to the integral/area under response peak. In a contrast to double integration ADC, the SumInt ADC integrates input signal continuously and does not require reset/idle interval control. In comparison to sigma-delta ADC, the frequency of reference switching is much lower (less charge leakage). The paid price is sampling interval floating in a range of up to one half of the fixed modulator interval. The actual ESA funded De-Risk project focuses on reuse of the technique for low analog components count conversion in radiation tolerant systems where FPGAs are already in use.
Czech name
—
Czech description
—

Publication year
2022
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Similar results(10)