Precise Subclock Period Delay in Digital Radar Target Simulation

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F25%3A00379915" target="_blank" >RIV/68407700:21230/25:00379915 - isvavai.cz</a>
Result on the web
<a href="http://hdl.handle.net/10467/125825" target="_blank" >http://hdl.handle.net/10467/125825</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/TIM.2025.3546412" target="_blank" >10.1109/TIM.2025.3546412</a>

Result language
angličtina
Original language name
Precise Subclock Period Delay in Digital Radar Target Simulation
Original language description
In the digital radar target simulation, the period of the digital signal processing clock determines the tiniest step in signal delay. The signal delay determines the range of the simulated target. Therefore, the step in signal delay corresponds to the range resolution of the target simulator. This paper proposes three methods on how to increase signal delay resolution in the digital domain below the clock period. The improvement is from resolution in the range of tens of centimeters to several millimeters. The first technique optimizes the organization of the sample stream. The second is based on the deployment of the tapped delay line. And the third method utilizes precise phase shifting of the sampling clock. The proposed techniques can be combined to achieve the desired delay resolution. The methods are implemented and evaluated on an FPGA-based automotive radar target simulator in the 80 GHz band.
Czech name
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Czech description
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Type
J<sub>imp</sub> - Article in a specialist periodical, which is included in the Web of Science database
CEP classification
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OECD FORD branch
20201 - Electrical and electronic engineering

Project
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Continuities
I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Publication year
2025
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

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