Fast Neural Network Implementation

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F99%3A03020682" target="_blank" >RIV/68407700:21230/99:03020682 - isvavai.cz</a>

Alternative codes found

RIV/68407700:21230/99:00060682

Result on the web

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DOI - Digital Object Identifier

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Result language

angličtina

Original language name

Fast Neural Network Implementation

Original language description

This article is focused on implementation of neural networks in hardware. We give an overview of so-called shift-add neural atithmetics, which provides a complete set of functions suitable for fast perceptron and RBF neuron implementations. The functionsuse linear approximation to reach sufficient simplicity. We show gate-level implementation of all functions based only on adders and shifters. Real implementations in FPGA XILINX and silicon chip are also presented.

Czech name

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Czech description

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Type

J_x - Unclassified - Peer-reviewed scientific article (Jimp, Jsc and Jost)

CEP classification

JC - Computer hardware and software

OECD FORD branch

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Project

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Continuities

Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year

1999

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Name of the periodical

Neural Network World

ISSN

1210-0552

e-ISSN

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Volume of the periodical

9

Issue of the periodical within the volume

5

Country of publishing house

CZ - CZECH REPUBLIC

Number of pages

17

Pages from-to

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UT code for WoS article

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EID of the result in the Scopus database

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