Design of scalable structures with defined dependability for system on chip
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F10%3A00167410" target="_blank" >RIV/68407700:21240/10:00167410 - isvavai.cz</a>
Alternative codes found
RIV/68407700:21230/10:00166068
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Design of scalable structures with defined dependability for system on chip
Original language description
This paper summarizes previous work, which observed design finite state machines of MOORE type with self-checking architecture. My concept is proved on a practical problem, which is implementing the railway station system in the FPGA. The safety device for any configuration of railway station can be built from five basic blocks. Each block is based on a finite state machine of MOORE type. My methodology is intended for final implementation in FPGA and hence SEU faults occurring in the system is assumed.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
<a href="/en/project/GA102%2F09%2F1668" target="_blank" >GA102/09/1668: SoC circuits reliability and availability improvement</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2010
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Workshop 2010
ISBN
978-80-01-04513-8
ISSN
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e-ISSN
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Number of pages
2
Pages from-to
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Publisher name
České vysoké učení technické v Praze
Place of publication
Praha
Event location
Praha
Event date
Feb 22, 2010
Type of event by nationality
EUR - Evropská akce
UT code for WoS article
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