Self Repair Architectures Based on Partial Dynamic and Static Reconfiguration
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F11%3A00183911" target="_blank" >RIV/68407700:21240/11:00183911 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Self Repair Architectures Based on Partial Dynamic and Static Reconfiguration
Original language description
This paper deals with a description of the method, how to increase dependability parameters (safety and reliability) of a system based on programmable hardware (FPGAs). This paper combines Concurrent Error Detection (CED) techniques, FPGA dynamic reconfigurations and our Modified Duplex System (MDS) architecture. The methodology is developed with respect to minimal area overhead and possible future low-power SoC (System on a chip) design. Our proposed methodology is great intended for practical applications, therefore our methodology is evaluated by safety railway station system. It is aimed especially for modular systems. The method is based on static and partial dynamic reconfiguration of totally self-checking blocks. The type and size of blocks to reconfigure depends on the used architecture and on the particular construction of a safety device for the particular railway station.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
<a href="/en/project/GA102%2F09%2F1668" target="_blank" >GA102/09/1668: SoC circuits reliability and availability improvement</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach
Others
Publication year
2011
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceeding of the 7th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science
ISBN
978-80-214-4305-1
ISSN
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e-ISSN
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Number of pages
8
Pages from-to
11-18
Publisher name
Brno University of Technology
Place of publication
Brno
Event location
Lednice
Event date
Oct 14, 2011
Type of event by nationality
CST - Celostátní akce
UT code for WoS article
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