Simulation and SAT Based ATPG for Compressed Test Generation
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F13%3A00207553" target="_blank" >RIV/68407700:21240/13:00207553 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1109/DSD.2013.56" target="_blank" >http://dx.doi.org/10.1109/DSD.2013.56</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DSD.2013.56" target="_blank" >10.1109/DSD.2013.56</a>
Alternative languages
Result language
angličtina
Original language name
Simulation and SAT Based ATPG for Compressed Test Generation
Original language description
This paper presents a novel ATPG algorithm directly producing compressed test patterns. It benefits both from the features of satisfiability-based techniques and symbolic simulation. The ATPG is targeted to architectures comprised of interconnected embedded cores, particularly to the RESPIN architecture. We show experimentally that the proposed ATPG significantly outperforms the state-of-the-art approaches in terms of the test compression ratio.
Czech name
—
Czech description
—
Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
—
Result continuities
Project
—
Continuities
S - Specificky vyzkum na vysokych skolach<br>I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace
Others
Publication year
2013
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of 16th Euromicro Conference on Digital System Design
ISBN
978-0-7695-5074-9
ISSN
—
e-ISSN
—
Number of pages
8
Pages from-to
445-452
Publisher name
IEEE Service Center
Place of publication
Piscataway
Event location
Santander
Event date
Sep 4, 2013
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000337235200060