Novel Error Detection and Correction Method Combining Time and Area Redundancy

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F15%3A00231270" target="_blank" >RIV/68407700:21240/15:00231270 - isvavai.cz</a>

Result on the web

<a href="http://pad2015.fai.utb.cz/sbornik.php" target="_blank" >http://pad2015.fai.utb.cz/sbornik.php</a>

DOI - Digital Object Identifier

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Result language

angličtina

Original language name

Novel Error Detection and Correction Method Combining Time and Area Redundancy

Original language description

In this paper, a novel fault-tolerant circuits design method is briefly described. It combines time and area redundancy to achieve error-correction abilities similar to triple-modular redundancy (TMR) and the area-overhead close to a duplex system. New logic gates design allowing complete stuck-at fault testability is presented.

Czech name

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Czech description

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Type

D - Article in proceedings

CEP classification

IN - Informatics

OECD FORD branch

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Project

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Continuities

S - Specificky vyzkum na vysokych skolach

Publication year

2015

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

Sborník příspěvků PAD 2015

ISBN

978-80-7454-522-1

ISSN

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e-ISSN

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Number of pages

6

Pages from-to

48-53

Publisher name

Universita Tomáše Bati ve Zlíně

Place of publication

Zlín

Event location

Zlín

Event date

Sep 2, 2015

Type of event by nationality

CST - Celostátní akce

UT code for WoS article

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