Novel C-Element Based Error Detection and Correction Method Combining Time and Area Redundancy
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F15%3A00231251" target="_blank" >RIV/68407700:21240/15:00231251 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1109/DSD.2015.95" target="_blank" >http://dx.doi.org/10.1109/DSD.2015.95</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DSD.2015.95" target="_blank" >10.1109/DSD.2015.95</a>
Alternative languages
Result language
angličtina
Original language name
Novel C-Element Based Error Detection and Correction Method Combining Time and Area Redundancy
Original language description
In this work we present a novel fault-tolerant circuits design method. It combines time and area redundancy to achieve error-correction abilities similar to a triple-modular redundancy (TMR) and the area-overhead close to a duplex system. New logic gates design allowing a complete stuck-at fault testability will be presented. Our method allows to test combinational parts of the circuit using a universal short-duration offline test. The offline-testable module with an online-checker allows to compose a fault-tolerant system with the mentioned properties. This system will be denoted as a time-extended duplex scheme. In this scheme the offline test is sufficiently short to allow error correction during the computation (paused pipeline). The presented method adopts some principles from dual-rail logic and asynchronous circuits design.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
20206 - Computer hardware and architecture
Result continuities
Project
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Continuities
S - Specificky vyzkum na vysokych skolach
Others
Publication year
2015
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the Euromicro Conference on Digital System Design - DSD 2015
ISBN
978-1-4673-8035-5
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
280-283
Publisher name
IEEE Computer Society
Place of publication
Los Alamitos
Event location
Funchal, Madeira
Event date
Aug 26, 2015
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000382382300041