All

What are you looking for?

All
Projects
Results
Organizations

Quick search

  • Projects supported by TA ČR
  • Excellent projects
  • Projects with the highest public support
  • Current projects

Smart search

  • That is how I find a specific +word
  • That is how I leave the -word out of the results
  • “That is how I can find the whole phrase”

Error Masking Method Based On The Short-Duration Offline Test

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F17%3A00312125" target="_blank" >RIV/68407700:21240/17:00312125 - isvavai.cz</a>

  • Result on the web

    <a href="http://dx.doi.org/10.1016/j.micpro.2017.06.007" target="_blank" >http://dx.doi.org/10.1016/j.micpro.2017.06.007</a>

  • DOI - Digital Object Identifier

    <a href="http://dx.doi.org/10.1016/j.micpro.2017.06.007" target="_blank" >10.1016/j.micpro.2017.06.007</a>

Alternative languages

  • Result language

    angličtina

  • Original language name

    Error Masking Method Based On The Short-Duration Offline Test

  • Original language description

    The method proposed in this article allows to construct error-masking fail-operational systems by com- bining time and area redundancy. In such a system, error detection is performed online, while error masking is achieved by a short-duration offline test. The time penalty caused by the offline test applies only when an error is detected. The error-masking ability in such a system is very close to TMR, the area overhead is smaller for a well defined class of circuits, and the delay penalty caused by the offline test remains reasonably small. The short-duration offline test is possible only when extensive design-for-test practices are used. Therefore, a novel gate structure is presented, which allows to construct combina- tional circuits testable by a short-duration offline test. The proposed test offers com plete fault coverage with respect to the stuck-on and stuck-open fault model. The proposed solutions are combined and a comprehensive description of the overall error-masking architecture is provided.

  • Czech name

  • Czech description

Classification

  • Type

    J<sub>imp</sub> - Article in a specialist periodical, which is included in the Web of Science database

  • CEP classification

  • OECD FORD branch

    20206 - Computer hardware and architecture

Result continuities

  • Project

    <a href="/en/project/GA16-05179S" target="_blank" >GA16-05179S: Fault-Tolerant and Attack-Resistant Architectures Based on Programmable Devices: Research of Interplay and Common Features</a><br>

  • Continuities

    P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Others

  • Publication year

    2017

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Name of the periodical

    Microprocessors and Microsystems

  • ISSN

    0141-9331

  • e-ISSN

    1872-9436

  • Volume of the periodical

    52

  • Issue of the periodical within the volume

    7

  • Country of publishing house

    NL - THE KINGDOM OF THE NETHERLANDS

  • Number of pages

    15

  • Pages from-to

    236-250

  • UT code for WoS article

    000407984000020

  • EID of the result in the Scopus database

    2-s2.0-85021293073