Novel Gate Design Method for Short-Duration Test
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F15%3A00232444" target="_blank" >RIV/68407700:21240/15:00232444 - isvavai.cz</a>
Result on the web
<a href="http://radio.feld.cvut.cz/conf/poster2015/" target="_blank" >http://radio.feld.cvut.cz/conf/poster2015/</a>
DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Novel Gate Design Method for Short-Duration Test
Original language description
In this paper, a novel logic gate design method will be presented. This method allows to test combinational parts of the circuit using a short-duration offline test. Short-duration offline tests are usable when fault-recovery in duplex-based systems is required and downtime should be minimized at the same time. The presented method adopts some principles from dual-rail logic and asynchronous circuits design.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
IN - Informatics
OECD FORD branch
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Result continuities
Project
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Continuities
S - Specificky vyzkum na vysokych skolach
Others
Publication year
2015
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the 19th International Scientific Student Conferenece POSTER 2015
ISBN
978-80-01-05499-4
ISSN
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e-ISSN
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Number of pages
5
Pages from-to
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Publisher name
Czech Technical University in Prague
Place of publication
Praha
Event location
Praha
Event date
May 14, 2015
Type of event by nationality
EUR - Evropská akce
UT code for WoS article
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