Automatic Generation of 100 Gbps Packet Parsers from P4 Description
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F15%3A00235676" target="_blank" >RIV/68407700:21240/15:00235676 - isvavai.cz</a>
Result on the web
<a href="http://h2rc.cse.sc.edu/h2rc-p2.pdf" target="_blank" >http://h2rc.cse.sc.edu/h2rc-p2.pdf</a>
DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Automatic Generation of 100 Gbps Packet Parsers from P4 Description
Original language description
Software Defined Networking and OpenFlow offer an elegant way to decouple network control plane from data plane. This decoupling has led to great innovation in the control plane, yet the data plane changes come at much slower pace, mainly due to the hard-wired implementation of network switches. The P4 language aims to overcome this obstacle by providing a description of a customized packet processing functionality for configurable switches. That enables a new generation of possibly heterogeneous networking hardware that can be run-time tailored for the needs of particular applications from various domains, such as HPC. In this paper we contribute to the idea of P4 by presenting design, analysis and experimental results of our packet parser generator.The generator converts a parse graph description of P4 to a synthetizable VHDL code suitable for FPGA implementation. Our results show that the generated circuit is able to parse 100 Gbps traffic with fairly complex protocol structure at
Czech name
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Czech description
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Classification
Type
O - Miscellaneous
CEP classification
IN - Informatics
OECD FORD branch
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Result continuities
Project
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Continuities
I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace
Others
Publication year
2015
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů