P4-to-VHDL: Automatic Generation of 100 Gbps Packet Parsers

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F63839172%3A_____%2F16%3A10130695" target="_blank" >RIV/63839172:_____/16:10130695 - isvavai.cz</a>
Alternative codes found
RIV/68407700:21240/16:00301150
Result on the web
<a href="http://dx.doi.org/10.1109/FCCM.2016.46" target="_blank" >http://dx.doi.org/10.1109/FCCM.2016.46</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/FCCM.2016.46" target="_blank" >10.1109/FCCM.2016.46</a>

Result language
angličtina
Original language name
P4-to-VHDL: Automatic Generation of 100 Gbps Packet Parsers
Original language description
Software Defined Networking and OpenFlow offer an elegant way to decouple network control plane from data plane. This decoupling has led to great innovation in the control plane, yet the data plane changes come at much slower pace, mainly due to the hard-wired implementation of network switches. The P4 language aims to overcome this obstacle by providing a description of a customized packet processing functionality for configurable switches. That enables a new generation of possibly heterogeneous networking hardware that can be run-time tailored for the needs of particular applications from various domains. In this paper we contribute to the idea of P4 by presenting design, analysis and experimental results of our packet parser generator. The generator converts a parse graph description of P4 to a synthetizable VHDL code suitable for FPGA implementation. Our results show that the generated circuit is able to parse 100 Gbps traffic with fairly complex protocol structure at line rate on a Xilinx Virtex-7 FPGA. The approach can be used not only in switches, but also in other appliances, such as application accelerators and smart NICs. We compare the generated output to a hand-written parser to show that the price for configurability is only a slightly larger and slower circuit.
Czech name
—
Czech description
—

Publication year
2016
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines
ISBN
978-1-5090-2356-1
ISSN
—
e-ISSN
—
Number of pages
8
Pages from-to
148-155
Publisher name
IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA
Place of publication
Washington, DC, USA
Event location
Washington, DC, USA
Event date
May 1, 2016
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000389602200037

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