A Rule-Based Approach for Minimizing Power Dissipation of Digital Circuits
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F16%3A00242677" target="_blank" >RIV/68407700:21240/16:00242677 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1109/DDECS.2016.7482470" target="_blank" >http://dx.doi.org/10.1109/DDECS.2016.7482470</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DDECS.2016.7482470" target="_blank" >10.1109/DDECS.2016.7482470</a>
Alternative languages
Result language
angličtina
Original language name
A Rule-Based Approach for Minimizing Power Dissipation of Digital Circuits
Original language description
Minimization of power dissipation of VLSI circuits is one of the major concerns of recent digital circuit design primarily due to the ever decreasing feature sizes of circuits, higher clock frequencies and larger die sizes. The primary contributors to power dissipation in digital circuits include leakage power, short-circuit power and switching power. Of these, power dissipation due to the circuit switching activity constitutes the major component. As such, an effective mechanism to minimize the power loss in such cases often involves the minimization of the switching activity. In this paper, we propose an intelligent rule-based algorithm for reducing the switching activity of the digital circuits at logic optimization stage. The proposed algorithm is empirically tested for several standard digital circuits with Synopsys EDA tool and the results obtained are quite encouraging.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
<a href="/en/project/GA16-05179S" target="_blank" >GA16-05179S: Fault-Tolerant and Attack-Resistant Architectures Based on Programmable Devices: Research of Interplay and Common Features</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2016
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
ISBN
978-1-5090-2467-4
ISSN
2334-3133
e-ISSN
—
Number of pages
6
Pages from-to
237-242
Publisher name
IEEE
Place of publication
Piscataway
Event location
Košice
Event date
Apr 20, 2016
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000387091100044