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Minimization of Switching Activity of Graphene Based Circuits

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F21%3A00349905" target="_blank" >RIV/68407700:21240/21:00349905 - isvavai.cz</a>

  • Result on the web

    <a href="https://doi.org/10.1109/VLSID51830.2021.00029" target="_blank" >https://doi.org/10.1109/VLSID51830.2021.00029</a>

  • DOI - Digital Object Identifier

    <a href="http://dx.doi.org/10.1109/VLSID51830.2021.00029" target="_blank" >10.1109/VLSID51830.2021.00029</a>

Alternative languages

  • Result language

    angličtina

  • Original language name

    Minimization of Switching Activity of Graphene Based Circuits

  • Original language description

    Reduction of power dissipation is a key challenge of VLSI circuits designers. In traditional CMOS-based circuits, dynamic power dissipation occurs due to the switching activity, i.e., transitions at logic nodes. In graphene-based circuits, power dissipation is also caused by the switching activity. In this paper, we compute the switching activity of these circuits considering the switching at every transistor. We propose an algorithm to minimize the total switching activity of graphene-based logic circuits. The algorithm is tested on benchmark circuits and the results show the reduction of average switching activity, area, and switching activity x area respectively by 9,17%, 0,81%, and 9,82%.

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

  • OECD FORD branch

    20206 - Computer hardware and architecture

Result continuities

  • Project

    <a href="/en/project/EF16_019%2F0000765" target="_blank" >EF16_019/0000765: Research Center for Informatics</a><br>

  • Continuities

    P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Others

  • Publication year

    2021

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    Proc. of the 34th International Conference on VLSI Design

  • ISBN

    978-1-6654-4087-5

  • ISSN

    1063-9667

  • e-ISSN

    1063-9667

  • Number of pages

    6

  • Pages from-to

    139-144

  • Publisher name

    IEEE

  • Place of publication

    Piscataway (New Jersey)

  • Event location

    Guwahati (virtual)

  • Event date

    Feb 20, 2021

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article

    000672616100025