Design Objectives for Synthesis of Graphene PN Junction Circuits based on Two-level Representation
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F24%3A00378095" target="_blank" >RIV/68407700:21240/24:00378095 - isvavai.cz</a>
Result on the web
<a href="https://doi.org/10.1109/DSD64264.2024.00011" target="_blank" >https://doi.org/10.1109/DSD64264.2024.00011</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DSD64264.2024.00011" target="_blank" >10.1109/DSD64264.2024.00011</a>
Alternative languages
Result language
angličtina
Original language name
Design Objectives for Synthesis of Graphene PN Junction Circuits based on Two-level Representation
Original language description
The development of electrostatically doped graphene PN-junctions shows promise for creating efficient low-power, high-speed circuits. In recent years, there has been a considerable interest in the synthesis of graphene PN junction logic circuits. However, existing synthesis methods lack assessment based on technology-specific cost metrics (e.g., the number of graphene PN junction gates, constant inputs), leading to insufficiently addressed design objectives. In this paper, we introduce synthesis approaches for graphene PN-junction circuits based on Sum-of-Products (SoP) and Exclusive Sum-of-Products (ESoP) function representations. Experimental results indicate that ESoP-based synthesis significantly reduces the number of graphene PN junction gates, constant inputs, and switching activity compared to SoP-based approaches. Overall, ESoP-based synthesis is deemed more suitable than SoP-based methods for designing graphene PN-junction logic circuits.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
—
OECD FORD branch
20206 - Computer hardware and architecture
Result continuities
Project
—
Continuities
I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace
Others
Publication year
2024
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the 2024 27th Euromicro Conference on Digital System Design
ISBN
979-8-3503-8038-5
ISSN
2639-3859
e-ISSN
2771-2508
Number of pages
8
Pages from-to
11-18
Publisher name
IEEE Computer Society
Place of publication
Los Alamitos
Event location
Paris
Event date
Aug 28, 2024
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
001414927800002