Area and Speed Oriented Implementations of Asynchronous Logic Operating Under Strong Constraints

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F10%3A00169329" target="_blank" >RIV/68407700:21240/10:00169329 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Area and Speed Oriented Implementations of Asynchronous Logic Operating Under Strong Constraints
Original language description
Asynchronous circuit implementations operating under strong constraints (DIMS, Direct Logic, some of NCL gates, etc.) are attractive due to: 1) regularity; 2) combined implementation of the functional and completion detection logics, what simplifies thedesign process; 3) circuit output latency is based on the actual gate delays of the unbounded nature; 4) absence of additional synchronization chains (even of a local nature). However, the area and speed penalty is rather high. In contrast to the state-of-the-art approaches, where simple (NAND, NOR, etc.) 2 input gates are used, we propose a synthesis method based on complex nodes, i.e., nodes implementing any function of an arbitrary number of inputs. Synchronous synthesis procedures may be freely adopted for this purpose.
Czech name
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Czech description
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Project
<a href="/en/project/GA102%2F09%2F1668" target="_blank" >GA102/09/1668: SoC circuits reliability and availability improvement</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year
2010
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the 13th Euromicro Conference on Digital System Design
ISBN
978-0-7695-4171-6
ISSN
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e-ISSN
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Number of pages
8
Pages from-to
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Publisher name
IEEE Computer Society Press
Place of publication
Los Alamitos
Event location
Lille
Event date
Sep 1, 2010
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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