Switching Activity Reduction in Graphene PN Junction Circuits using Circuit Re-structuring

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F23%3A00366489" target="_blank" >RIV/68407700:21240/23:00366489 - isvavai.cz</a>
Result on the web
<a href="https://doi.org/10.1109/ISDCS58735.2023.10153524" target="_blank" >https://doi.org/10.1109/ISDCS58735.2023.10153524</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/ISDCS58735.2023.10153524" target="_blank" >10.1109/ISDCS58735.2023.10153524</a>

Result language
angličtina
Original language name
Switching Activity Reduction in Graphene PN Junction Circuits using Circuit Re-structuring
Original language description
Graphene PN Junction (GPNJ) logic circuits received significant attention from the researchers thanks to the availability of electrostatically doped graphene PN Junction (GPNJ) device- a promising one for designing low-power, high-speed circuits. Several design approaches for GPNJ logic circuits realizing important arithmetic and arbitrary Boolean functions exist in literature. However, no detailed evaluations of the resulting circuit complexities with respect to relevant cost metrics are reported. It remains open, how do we synthesize GPNJ logic circuits with minimal switching activity, an essential cost metric influencing the dynamic power dissipation in the resulting circuits. In this paper, we introduce a synthesis approach for GPNJ logic circuits that interconnects a set of GPNJ devices in parallel. Such parallel circuit structures ensure the reduction of switching activity in the resulting GPNJ logic circuits. To the best of our knowledge, so far only one research work discussed the computation of switching activity of GPNJ logic circuits. Experimental evaluations confirm that an average 67.35% reduction in switching activity can be achieved using the proposed approach over the existing one.
Czech name
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Czech description
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Project
<a href="/en/project/EF16_019%2F0000765" target="_blank" >EF16_019/0000765: Research Center for Informatics</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year
2023
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the 6th International Symposium on Devices, Circuits and Systems
ISBN
979-8-3503-1504-2
ISSN
2767-9837
e-ISSN
2767-9837
Number of pages
6
Pages from-to
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Publisher name
Hiroshima University
Place of publication
Hiroshima
Event location
Virtual conference
Event date
May 29, 2023
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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