Influence of Fault-tolerant Design Methods on Resistance against Differential Power Analysis in FPGA
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F16%3A00304261" target="_blank" >RIV/68407700:21240/16:00304261 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Influence of Fault-tolerant Design Methods on Resistance against Differential Power Analysis in FPGA
Original language description
Many electronic systems has to fulfill strict dependability properties, especially both fault-tolerance and attack-resistance. There are many digital design methods increasing these two properties, but these methods usualy cost high area and power consumption overhead. This overhead is even higher when we demand both of these properties. Our objective is to propose new design methods for both fault-tolerant and attack-resistant digital design at the same time in order to decrease the overhead.
Czech name
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Czech description
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Classification
Type
O - Miscellaneous
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
<a href="/en/project/GA16-05179S" target="_blank" >GA16-05179S: Fault-Tolerant and Attack-Resistant Architectures Based on Programmable Devices: Research of Interplay and Common Features</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2016
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů