The State-of-the-Art of the Logic representations for the synthesis
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F17%3A00308450" target="_blank" >RIV/68407700:21240/17:00308450 - isvavai.cz</a>
Result on the web
—
DOI - Digital Object Identifier
—
Alternative languages
Result language
angličtina
Original language name
The State-of-the-Art of the Logic representations for the synthesis
Original language description
This report summarizes the State-of-the-Art in the logic synthesis representations. The representation by Sum of Products (SOPs) was used in first synthesis EDA tools. Later, a representation based on binary decision tree, BDD, has been introduced. However, these representations were not scallable. To address scalability AIGs were implemented in academic synthesis tool ABC, which seemed to be an ultimate solution to the synthesis. However circuits for which ABC synthesis is weak have been found. New representation based on AIG and BDD, namely MIGs, XMGs and BBDDs were created as an attempt to help synthesis process to optimize networks efficiently.
Czech name
—
Czech description
—
Classification
Type
O - Miscellaneous
CEP classification
—
OECD FORD branch
20206 - Computer hardware and architecture
Result continuities
Project
<a href="/en/project/GA16-05179S" target="_blank" >GA16-05179S: Fault-Tolerant and Attack-Resistant Architectures Based on Programmable Devices: Research of Interplay and Common Features</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2017
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů