EA-based refactoring of mapped logic circuits
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F19%3APU132968" target="_blank" >RIV/00216305:26230/19:PU132968 - isvavai.cz</a>
Result on the web
<a href="https://www.fit.vut.cz/research/publication/11847/" target="_blank" >https://www.fit.vut.cz/research/publication/11847/</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/ISCAS.2019.8702084" target="_blank" >10.1109/ISCAS.2019.8702084</a>
Alternative languages
Result language
angličtina
Original language name
EA-based refactoring of mapped logic circuits
Original language description
The increasing complexity of the designs and prob-lematic scalability of original representations led to a shift ininternal representations used in logic synthesis and optimization. Heterogeneous representations were replaced with homogeneous intermediate representations. And-inverter graph (AIG) has been identified as the most promising structure for scalable logic optimization and many efficient algorithms were implemented on top of it. However, the inability of AIG to efficiently represent XOR gates together with heuristic nature of logic optimization algorithms leads to some inefficiency causing that the logic can be further minimized even after it has been mapped. This paper presents an optimization technique based on refactoring targeting mapped combinational circuits. It iteratively selects large cones of logic, optimizes them and returns them back to the original structure provided that there is an improvement in some metric.Performance of the method is evaluated on a set of complex academic and industrial benchmarks. We show that a 9.2%reduction in area can be achieved in average compared to thehighly optimized results obtained using the academic state-of-the-art synthesis tool. In average, more than 14% reduction was observed for arithmetic circuits.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)
Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2019
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
2019 IEEE International Symposium on Circuits and Systems (ISCAS)
ISBN
978-1-7281-0397-6
ISSN
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e-ISSN
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Number of pages
5
Pages from-to
1-5
Publisher name
IEEE Computer Society Press
Place of publication
Red Hook, NY
Event location
Sapporo
Event date
May 26, 2019
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000483076400021