Resynthesis of logic circuits using machine learning and reconvergent paths

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F21%3APU142903" target="_blank" >RIV/00216305:26230/21:PU142903 - isvavai.cz</a>

Result on the web

<a href="https://www.fit.vut.cz/research/publication/12490/" target="_blank" >https://www.fit.vut.cz/research/publication/12490/</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/DSD53832.2021.00020" target="_blank" >10.1109/DSD53832.2021.00020</a>

Result language

angličtina

Original language name

Resynthesis of logic circuits using machine learning and reconvergent paths

Original language description

Boolean network scoping represents a common approach incorporated in conventional synthesis tools for maintaining good scalability of the synthesis process. Recently, an approach to the local resynthesis based on combination of evolutionary optimization with the principle of Boolean network scoping has been proposed. Local resynthesis is an iterative process based on the extraction of smaller sub-circuits from a complex circuit that are optimized locally and implanted back to the original circuit. The main advantage of the local resynthesis is that it can mitigate the problem of scalability of representation which is typical to the evolutionary algorithms as the efficiency of the evolutionary optimization applied at the global level deteriorates with the increasing circuit complexity. Unfortunately, the efficiency of local resynthesis depends on the efficiency of the sub-circuit extraction process. We propose an alternative method, based on the reconvergent paths. The evaluation is performed on a set of highly optimized benchmark problems representing various real-world controllers, logic and arithmetic circuits. The method provides better results compared to the state-of-the-art logic synthesis tool and evolutionary optimization techniques operating locally and globally. A substantially higher number of redundant gates was removed in more than 70% cases, while keeping the computational effort at the same level. A huge improvement was achieved especially for the controllers. On average, the proposed method was able to remove more than 14.3% of gates. The highest achieved gate reduction was more than 45% of gates.

Czech name

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Czech description

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Type

D - Article in proceedings

CEP classification

—

OECD FORD branch

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Project

<a href="/en/project/GA19-10137S" target="_blank" >GA19-10137S: Designing and exploiting libraries of approximate circuits</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2021

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

2021 24th Euromicro Conference on Digital System Design (DSD)

ISBN

978-1-6654-2704-3

ISSN

—

e-ISSN

—

Number of pages

8

Pages from-to

69-76

Publisher name

Institute of Electrical and Electronics Engineers

Place of publication

Palermo

Event location

Palermo

Event date

Sep 1, 2021

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

000728394500011