Impact of subcircuit selection on the efficiency of CGP-based optimization of gate-level circuits

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F19%3APU132975" target="_blank" >RIV/00216305:26230/19:PU132975 - isvavai.cz</a>

Result on the web

<a href="https://www.fit.vut.cz/research/publication/11921/" target="_blank" >https://www.fit.vut.cz/research/publication/11921/</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1145/3319619.3321926" target="_blank" >10.1145/3319619.3321926</a>

Result language

angličtina

Original language name

Impact of subcircuit selection on the efficiency of CGP-based optimization of gate-level circuits

Original language description

Various EA-based methods have been applied to design and optimize logic circuits since the early nineties. The unconventional methods, however, typically suffer from various scalability issues preventing them to be adopted in practice. Recent improvement in the fitness computation procedure connected with the introduction of formal methods in the fitness evaluation such as SAT solvers or BDDs enabled pushing of the limits forward and approaching the complexity of industrial problems. It was demonstrated that EAs can be applied to optimize gate-level circuits consisting of thousands of gates without introducing any decomposition technique. Despite that, the efficiency decreases with increasing the circuit complexity. This problem can be managed by adopting the concept of the so-called iterative resynthesis based on the extraction of smaller sub-circuits from a complex circuit, their local optimization followed by the implantation back to the original circuit. Recently, a method based on the computation of so-called cuts was proposed. In this paper, we propose an alternative approach which is able to select more complex sub-graphs consisting of more nodes and more inputs. Compared to the previous method, the proposed approach allows to improve the efficiency of the optimization. More than 9% and 20% reduction was observed on the highly optimized logic and arithmetic circuits, respectively.

Czech name

—

Czech description

—

Type

D - Article in proceedings

CEP classification

—

OECD FORD branch

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Project

Result was created during the realization of more than one project. More information in the Projects tab.

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Publication year

2019

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

GECCO '19 Proceedings of the Genetic and Evolutionary Computation Conference Companion

ISBN

978-1-4503-6748-6

ISSN

—

e-ISSN

—

Number of pages

2

Pages from-to

377-378

Publisher name

Association for Computing Machinery

Place of publication

New York

Event location

Praha

Event date

Jul 13, 2019

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

000538328100188