EA-based Resynthesis: An Efficient Tool for Optimization of Digital Circuits
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F20%3APU138645" target="_blank" >RIV/00216305:26230/20:PU138645 - isvavai.cz</a>
Result on the web
<a href="https://www.fit.vut.cz/research/publication/12104/" target="_blank" >https://www.fit.vut.cz/research/publication/12104/</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1007/s10710-020-09376-3" target="_blank" >10.1007/s10710-020-09376-3</a>
Alternative languages
Result language
angličtina
Original language name
EA-based Resynthesis: An Efficient Tool for Optimization of Digital Circuits
Original language description
Since the early nineties the lack of scalability of fitness evaluation has been the main bottleneck preventing the adoption of evolutionary algorithms for logic circuits synthesis. Recently, various formal approaches such as SAT and BDD solvers have been introduced to this field to overcome this issue. This made it possible to optimise complex circuits consisting of hundreds of inputs and thousands of gates. Unfortunately, we are facing another problem-scalability of representation. The efficiency of the evolutionary optimization applied at the global level deteriorates with the increasing complexity. To overcome this issue, we propose to apply the concept of local resynthesis in this work. Local resynthesis is an iterative process based on the extraction of smaller sub-circuits from a complex circuit that are optimized locally and implanted back to the original circuit. When applied appropriately, this approach can mitigate the problem of scalability of representation. Two complementary approaches to the extraction of the sub-circuits are presented and evaluated in this work. The evaluation is done on a set of highly optimized complex benchmark problems representing various real-world controllers, logic and arithmetic circuits. The experimental results show that the evolutionary resynthesis provides better results compared to globally operating evolutionary optimization. In more than 85% cases, a substantially higher number of redundant gates was removed while keeping the computational effort at the same level. A huge improvement was achieved especially for the arithmetic circuits. On average, the proposed method was able to remove 25.1% more gates.
Czech name
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Czech description
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Classification
Type
J<sub>imp</sub> - Article in a specialist periodical, which is included in the Web of Science database
CEP classification
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OECD FORD branch
10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)
Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2020
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Name of the periodical
Genetic Programming and Evolvable Machines
ISSN
1389-2576
e-ISSN
1573-7632
Volume of the periodical
21
Issue of the periodical within the volume
3
Country of publishing house
US - UNITED STATES
Number of pages
33
Pages from-to
287-319
UT code for WoS article
000510271200002
EID of the result in the Scopus database
2-s2.0-85078849825