Optimization of Pearson correlation coefficient calculation for DPA and comparison of different approaches
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F17%3A00311675" target="_blank" >RIV/68407700:21240/17:00311675 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1109/DDECS.2017.7934563" target="_blank" >http://dx.doi.org/10.1109/DDECS.2017.7934563</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DDECS.2017.7934563" target="_blank" >10.1109/DDECS.2017.7934563</a>
Alternative languages
Result language
angličtina
Original language name
Optimization of Pearson correlation coefficient calculation for DPA and comparison of different approaches
Original language description
Differential power analysis (DPA) is one of the most common side channel attacks. To perform this attack we need to calculate a large amount of correlation coefficients. This amount is even higher when attacking FPGAs or ASICs, for higher order attacks and especially for attacking DPA protected devices. This article explains different approaches to the calculation of correlations, describes our implementation of these approaches and presents a detailed comparison considering their performance and their properties for a practical usage.
Czech name
—
Czech description
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Classification
Type
D - Article in proceedings
CEP classification
—
OECD FORD branch
20206 - Computer hardware and architecture
Result continuities
Project
<a href="/en/project/GA16-05179S" target="_blank" >GA16-05179S: Fault-Tolerant and Attack-Resistant Architectures Based on Programmable Devices: Research of Interplay and Common Features</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2017
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the 2017 IEEE 20th International Symposium on Design and Diagnotics of Electronic Circuit & Systems
ISBN
978-1-5386-0472-4
ISSN
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e-ISSN
2473-2117
Number of pages
6
Pages from-to
184-189
Publisher name
IEEE
Place of publication
Piscataway, NJ
Event location
Dresden
Event date
Apr 19, 2017
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000403405200033