Speeding up differential power analysis using integrated power traces

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F18%3A00322050" target="_blank" >RIV/68407700:21240/18:00322050 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Speeding up differential power analysis using integrated power traces
Original language description
Side-channel attacks, including differential power analysis (DPA), are still an emerging topic. To make a deep research about DPA, one needs to be able to perform it as fast as possible. There are many possible ways to decrease the time of the attack. In this paper, we propose a way to decrease the duration of the correlation computations of this kind of attack by decreasing the number of samples per a power trace using an integration based aggregation method. We comprehensively describe this idea and present the results of an experimental evaluation focusing on the time efficiency of this approach.
Czech name
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Czech description
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Project
<a href="/en/project/GA16-05179S" target="_blank" >GA16-05179S: Fault-Tolerant and Attack-Resistant Architectures Based on Programmable Devices: Research of Interplay and Common Features</a><br>
Continuities
S - Specificky vyzkum na vysokych skolach

Publication year
2018
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
2018 7th Mediterranean Conference on Embedded Computing (MECO)
ISBN
978-1-5386-5683-9
ISSN
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e-ISSN
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Number of pages
5
Pages from-to
19-23
Publisher name
IEEE
Place of publication
Piscataway
Event location
Budva
Event date
Jun 10, 2018
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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