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SAT-Based Generation of Optimum Function Implementations with XOR Gates

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F17%3A00312886" target="_blank" >RIV/68407700:21240/17:00312886 - isvavai.cz</a>

  • Result on the web

    <a href="http://dx.doi.org/10.1109/DSD.2017.74" target="_blank" >http://dx.doi.org/10.1109/DSD.2017.74</a>

  • DOI - Digital Object Identifier

    <a href="http://dx.doi.org/10.1109/DSD.2017.74" target="_blank" >10.1109/DSD.2017.74</a>

Alternative languages

  • Result language

    angličtina

  • Original language name

    SAT-Based Generation of Optimum Function Implementations with XOR Gates

  • Original language description

    This paper presents a method for generating optimum multi-level implementations of Boolean functions. It is based on Satisfiability (SAT) problem solving, while different SAT techniques are employed to reach different targets. The method is able to generate one, or enumerate all optimum implementations, while any technology constraints can be applied. Results for 4 input functions implemented by XOR AND-Inverter-Graphs (XAIGs) with different XOR nodes costs are presented. Scalability and feasibility of the method is presented. Finally, an experimental evaluation of XAIG based rewriting algorithm with optimum replacement circuits is presented and compared with the previous solution.

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

  • OECD FORD branch

    20206 - Computer hardware and architecture

Result continuities

  • Project

    <a href="/en/project/GA16-05179S" target="_blank" >GA16-05179S: Fault-Tolerant and Attack-Resistant Architectures Based on Programmable Devices: Research of Interplay and Common Features</a><br>

  • Continuities

    P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Others

  • Publication year

    2017

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    Proc. of the 20th Euromicro Conference on Digital System Design

  • ISBN

    978-1-5386-2146-2

  • ISSN

  • e-ISSN

  • Number of pages

    8

  • Pages from-to

    163-170

  • Publisher name

    IEEE

  • Place of publication

    Piscataway, NJ

  • Event location

    Vienna

  • Event date

    Aug 30, 2017

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article

    000427097100022