Performance Comparison of Multiple Approaches of Status Register for Medium Density Memory Suitable for Implementation of a Lossless Compression Dictionary

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F18%3A00319225" target="_blank" >RIV/68407700:21240/18:00319225 - isvavai.cz</a>
Result on the web
<a href="https://dl.acm.org/citation.cfm?id=3174976" target="_blank" >https://dl.acm.org/citation.cfm?id=3174976</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1145/3174243.3174976" target="_blank" >10.1145/3174243.3174976</a>

Result language
angličtina
Original language name
Performance Comparison of Multiple Approaches of Status Register for Medium Density Memory Suitable for Implementation of a Lossless Compression Dictionary
Original language description
This paper presents a performance comparison of various approaches of realization of status register suitable for maintaining (in)valid bits in mid-density memory structures implemented in Xilinx FPGAs. An example of a such structure with status register could be a dictionary for Lempel-Ziv based lossless compression algorithms where the dictionary has to be initialized before each run of the algorithm with minimum time and logic resources consumption. The performance evaluation of designs has been made in Xilinx ISE and Vivado toolkits for the Virtex-7 FPGA. This research has been partially supported by the CTU project SGS17/017/OHK3/1T/18 "Dependable and attack-resistant architectures for programmable devices" and by the project "E-infrastructure CESNET "modernization" no. CZ.02.1.01/0.0/0.0/16 013/0001797.
Czech name
—
Czech description
—

Publication year
2018
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Similar results(10)