Design and implementation of sub 0.5-V OTAs in 0.18-m CMOS

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21460%2F18%3A00329545" target="_blank" >RIV/68407700:21460/18:00329545 - isvavai.cz</a>
Result on the web
<a href="https://onlinelibrary.wiley.com/doi/full/10.1002/cta.2465" target="_blank" >https://onlinelibrary.wiley.com/doi/full/10.1002/cta.2465</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1002/cta.2465" target="_blank" >10.1002/cta.2465</a>

Result language
angličtina
Original language name
Design and implementation of sub 0.5-V OTAs in 0.18-m CMOS
Original language description
A family of bulk-driven CMOS operational transconductance amplifiers (OTAs) has been designed for extremely low supply voltages (0.3-0.5V). Three OTA design schemes with different gain boosting techniques and class AB input/output stages are discussed. A detailed comparison among these schemes has been presented in terms of performance characteristics such as voltage gain, gain-bandwidth product, slew rate, circuit sensitivity to process/mismatch variations, and silicon area. The design procedures for all the compared structures have been developed. The OTAs have been fabricated in a standard 0.18-m n-well CMOS process from TSMC. Chip test results are in good agreement with theoretical predictions and simulations.
Czech name
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Czech description
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Type
J<sub>imp</sub> - Article in a specialist periodical, which is included in the Web of Science database
CEP classification
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OECD FORD branch
20201 - Electrical and electronic engineering

Project
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Continuities
I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Publication year
2018
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

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