A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta-Sigma Modulator in 0.18-mu m CMOS
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21460%2F19%3A00340713" target="_blank" >RIV/68407700:21460/19:00340713 - isvavai.cz</a>
Result on the web
<a href="https://doi.org/10.1109/TVLSI.2018.2878625" target="_blank" >https://doi.org/10.1109/TVLSI.2018.2878625</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/TVLSI.2018.2878625" target="_blank" >10.1109/TVLSI.2018.2878625</a>
Alternative languages
Result language
angličtina
Original language name
A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta-Sigma Modulator in 0.18-mu m CMOS
Original language description
A new solution for an ultralow-voltage bulk-driven (BD) asynchronous delta-sigma modulator is described in this paper. While implemented in a standard 0.18-mu m CMOS process from the Taiwan Semiconductor Manufacturing Company and supplied with V-DD = 0.3 V, the circuit offers a 53.3-dB signal-to-noise and distortion ratio, which corresponds to 8.56-bit resolution. In addition, the total power consumption is 37 nW, the signal bandwidth is 62 Hz, and the resulting power efficiency is 0.79 pJ/conversion. The above-mentioned features have been achieved employing a highly linear transconductor and a hysteretic comparator based on nontailed BD differential pair.
Czech name
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Czech description
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Classification
Type
J<sub>imp</sub> - Article in a specialist periodical, which is included in the Web of Science database
CEP classification
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OECD FORD branch
10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)
Result continuities
Project
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Continuities
I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace
Others
Publication year
2019
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Name of the periodical
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ISSN
1063-8210
e-ISSN
1557-9999
Volume of the periodical
27
Issue of the periodical within the volume
2
Country of publishing house
US - UNITED STATES
Number of pages
10
Pages from-to
316-325
UT code for WoS article
000458069300005
EID of the result in the Scopus database
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