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DFT Flow for RT Level Digital Circuits Using iFCoRT System
Our team performs some research activities at the field of testability in past years. These activities results in testability analysis, testability verification Circuits Testability). This paper describes how the s...
JC - Počítačový hardware a software
- 2006 •
- D
Rok uplatnění
D - Stať ve sborníku
Two-sided locally testable languages
We extend the two-sided strictly testable languages to the two-sided testable on SIgma^k, the family 2LTR(k) of k-R-testable languages is obtained as a special kind of Boolean closure of the family of two- sided strictly k-...
Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)
- 2018 •
- D •
- Link
Rok uplatnění
D - Stať ve sborníku
Výsledek na webu
Tools for split RTL circuit into Testable blocks
Developed tools make possible to split circuit written in formal model that was developed on DSC into Testable blocks and design scan chain. Outputs of tools are individual Testable blocks written in verilog....
JC - Počítačový hardware a software
- 2007 •
- X
Rok uplatnění
X - Nezařazeno
Methodology for Identification Testable Blocks in Circuit on RT Level
The concept of Testable block developed on formal model on RT level is presented in the paper. Principles of identification of Testable block are defined. In the next part the details of implementation of methodology is described. A...
JC - Počítačový hardware a software
- 2007 •
- D
Rok uplatnění
D - Stať ve sborníku
Testable Block Identification in RT Level Circuits
The formal model of Testable block on RT level is presented in the paper. Principles of identification of Testable block are defined. In the next part the details of implementation of methodology is described. At the end o...
JC - Počítačový hardware a software
- 2008 •
- D
Rok uplatnění
D - Stať ve sborníku
Testability Analysis Based on Formal Model
Formal model of a circuit on RT level is described in this paper. The model is used to describe properties of Testable Block. It is indicated how the concept of Testable Block can be used to reduce RT level test application time by ...
JC - Počítačový hardware a software
- 2006 •
- D
Rok uplatnění
D - Stať ve sborníku
Combat vehicles testability
Workshop of SINATS project. The paper is about trends in-vehicle networking, testability of military vehicles.
JY - Střelné zbraně, munice, výbušniny, bojová vozidla
- 2008 •
- D
Rok uplatnění
D - Stať ve sborníku
On Distribution of Testability Values in Scan-Layout State-Space
In the paper, it is shown how are testability values distributed within the scan-layout state-space for particular digital circuit. The goal of the paper was to approve or dismiss our hypothesis that the more registers are included in greate...
JC - Počítačový hardware a software
- 2006 •
- D
Rok uplatnění
D - Stať ve sborníku
Improving Testability Parameters of Pipelined Circuits Through the Identification of Testable Cores
A new methodology of selecting registers into scan chain is presented. It is based on the identification of testable cores. The methodology is supposed to be used preferably for pipelined circuits consisting of a high number of stages....
JC - Počítačový hardware a software
- 2004 •
- D
Rok uplatnění
D - Stať ve sborníku
Testability analysis and improvements of register-transfer level digital circuits
The paper deals with main topics and problems that are related to testability analysis of digital circuits. The main goal of the paper is to present both motivation and research goals as they were set in author's PhD thesis. In PhD thesis, a...
JC - Počítačový hardware a software
- 2004 •
- D
Rok uplatnění
D - Stať ve sborníku
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