PANACHE - Pilot line for Advanced Nonvolatile memory technologies for Automotive microControllers, High security applications and general Electronics
Public support
Provider
Ministry of Education, Youth and Sports
Programme
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Call for proposals
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Main participants
Ústav teorie informace a automatizace AV ČR, v. v. i.
Contest type
M2 - International cooperation
Contract ID
MSMT-16274/2014-1
Alternative language
Project name in Czech
PANACHE - Pilot line for Advanced Nonvolatile memory technologies for Automotive microControllers, High security applications and general Electronics
Annotation in Czech
The PANACHE project objective is to set-up a pilot line for embedded Flash technology design and manufacturing platform for the prototyping of innovative μcontrollers in Europe. The current 40nm technology platform as well as the already defined 55nm technology platform will be developed and consolidated in order to build a solid manufacturing platform on these technology nodes. The project will also extend to build the basic blocks of the technology node after 40nm; with the ambition to achieve a prototyping maturity for a new BEOL based non-volatile memory architecture suitable with the 28 nm node. To achieve this goal of generating high value added semiconductor circuits in Europe in a breakthrough leading edge technology the project will deploy all the necessary activities to bring a new technology to an early industrial maturity stage.
Scientific branches
R&D category
AP - Applied research
CEP classification - main branch
JA - Electronics and optoelectronics
CEP - secondary branch
JC - Computer hardware and software
CEP - another secondary branch
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OECD FORD - equivalent branches <br>(according to the <a href="http://www.vyzkum.cz/storage/att/E6EF7938F0E854BAE520AC119FB22E8D/Prevodnik_oboru_Frascati.pdf">converter</a>)
20201 - Electrical and electronic engineering<br>20206 - Computer hardware and architecture
Completed project evaluation
Provider evaluation
V - Vynikající výsledky projektu (s mezinárodním významem atd.)
Project results evaluation
The project objective was to set up a pilot line for embedded flash technology design and to manufacture a platform for the prototyping of innovative microcontrollers in Europe. The team developed the terminal for intelligent camera based on the chip with 90nm embeddded flash and ported this design to PANACHE chip with 40nm flash, evaluated and documented the prototype and successfuly evaluated the migration process from 90nm to the 40nm technology.
Solution timeline
Realization period - beginning
Jan 2, 2014
Realization period - end
Dec 31, 2017
Project status
U - Finished project
Latest support payment
Mar 2, 2017
Data delivery to CEP
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data delivery code
CEP18-MSM-7H-U/01:1
Data delivery date
Jun 11, 2018
Finance
Total approved costs
3,145 thou. CZK
Public financial support
2,674 thou. CZK
Other public sources
471 thou. CZK
Non public and foreign sources
0 thou. CZK