Fault Collapsing and Test Generation for a Circuits

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216224%3A14330%2F13%3A00065527" target="_blank" >RIV/00216224:14330/13:00065527 - isvavai.cz</a>

Result on the web

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DOI - Digital Object Identifier

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Result language

angličtina

Original language name

Fault Collapsing and Test Generation for a Circuits

Original language description

A novel method to generate a complete list of faults and their corresponding test vectors for a gate-level circuit is presented. This method creates the distinguishable faults of a circuit based on the paths they propagate, along with the test vector(s)for each fault. While the other available methods for fault list and test vector generation are expensive, this method tries to reduce the cost by avoiding all the unnecessary steps and merging the two tasks together.

Czech name

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Czech description

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Type

D - Article in proceedings

CEP classification

IN - Informatics

OECD FORD branch

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Project

<a href="/en/project/TA01011383" target="_blank" >TA01011383: Digital spectrometric system of nuclear radiation</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Publication year

2013

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

DETERIORATION, DEPENDABILITY, DIAGNOSTICS 2013

ISBN

9788072319398

ISSN

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e-ISSN

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Number of pages

7

Pages from-to

55-61

Publisher name

University of Defence, Faculty of Military Technology

Place of publication

Brno, Czech Republic

Event location

Brno, University of Defence, Sumavska 4

Event date

Oct 1, 2013

Type of event by nationality

EUR - Evropská akce

UT code for WoS article

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