Reduction of Test Vectors Number based on Parasitic Capacity Extraction of Scan Chain Wires

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F12%3APU101801" target="_blank" >RIV/00216305:26230/12:PU101801 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Reduction of Test Vectors Number based on Parasitic Capacity Extraction of Scan Chain Wires
Original language description
In this paper, method for scan chain optimisation performed after physical layout is presented. It is shown how the method can be used to decrease the number of test vectors. The principles of the method are based on parasitic capacity extraction, eliminating some bridging faults in the physical layout and subsequent reduction of the number of test vectors needed to test the circuit. The method was verified on circuits from benchmark set, experimental results are provided and discussed. It is expected that the method can be used in mass production of electronic components.
Czech name
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Czech description
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Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach

Publication year
2012
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of CSE 2012 International Scientific Conference on Computer Science and Engineering
ISBN
978-80-8143-049-7
ISSN
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e-ISSN
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Number of pages
8
Pages from-to
162-169
Publisher name
Faculty of Electrical Engineering and Informatics, University of Technology Košice
Place of publication
Košice
Event location
Stará Lesná
Event date
Oct 3, 2012
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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