Design of Phase Locked-Loop for Very Slow Sine-Wave Signals
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F08%3APU71521" target="_blank" >RIV/00216305:26220/08:PU71521 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Design of Phase Locked-Loop for Very Slow Sine-Wave Signals
Original language description
The paper describes the design procedure of phase locked loop (PLL). This PLL is used in band-pass sigma-delta modulator to synchronise the input slow sine-wave signal with driving clock of modulator. It generates 62,5 kHz rectangle driving signal. The paper also shows simulation results, which confirm the design process .
Czech name
Návrh fázového závěsu pro pomalé harmonické signály
Czech description
Článek popisuje návrh a vývoj fázového závěsu, který je určen pro synchronizaci s modulátorem sigma-delta.
Classification
Type
D - Article in proceedings
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
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Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2008
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of IEEE International Conference on Systems ICONS 2008
ISBN
978-0-7695-3105-2
ISSN
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e-ISSN
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Number of pages
5
Pages from-to
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Publisher name
IEEE
Place of publication
Cancun
Event location
Cancun
Event date
Apr 13, 2008
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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