Dynamic Partial Reconfiguration of FPGA
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F08%3APU76256" target="_blank" >RIV/00216305:26220/08:PU76256 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Dynamic Partial Reconfiguration of FPGA
Original language description
This paper deals with one possible way how to use dynamic partial reconfiguration (DPR) of FPGAs. In the first part main principles and problems of DPR are described. The second part of paper proposes one of the possible concepts of DPR usage. Reconfiguration is used for resources reallocation in order to adapt system to current workload in this concept. If FPGA is used as a hardware accelerator in static system, the tradeoff between chip area and performance can be done in design time only. Using DPR this tradeoff can be partly done during runtime also which is main idea of proposed concept.
Czech name
Dynamická částečná rekonfigurace FPGA
Czech description
Článek se zabývá využitím dynamické částečné rekonfigurace FPGA
Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
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Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2008
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
THE SEVENTH INTERNATIONAL PHD STUDENTS' WORKSHOP CONTROL & INFORMATION TECHNOLOGY IWCIT'08, EAN-9788390474380
ISBN
80-7078-907-7
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
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Publisher name
Silesian University of Technology
Place of publication
Gliwice, Poland
Event location
Gliwice
Event date
Sep 18, 2008
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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